Transmited light micrograph of an Intel Pentium microprocessor's clock driver, code cache and instruction fetch units. A 32-bit CPU with: a 64-bit data bus, 3.3 million transistors, 0.6 痠 manufacturing process, and superscalar architecture. The instruction cycles are regulated by the clock signals of the clock driver, which oscillates at 100 MHz. The chip has separate code cache and data cache units. The cache memory (SRAM) stores data so that future requests can be served faster. In the instruction fetch unit the instruction is fetched from the memory address. The chip was fabricated by photolithography, using several overlapping metalization layers and vertical contacts to interconnect them in a mono-crystal silicon wafer, which serves as the substrate. Field of view size: 2.97 x 4.45 mm (0.117 x 0.175 in)