Transmited light micrograph of an Intel Pentium microprocessor's instruction decode unit. A 32-Bit CPU with: a 64-bit data bus, 100 MHz operating frequency, 3.3 million transistors, 0.6 痠 manufacturing process, and superscalar architecture (two instructions per clock cycle). In each instruction cycle or fetch-decode-execute cycle the decode unit decodes the prefetched instructions for the processor to execute. The chip was fabricated by photolithography, using several overlapping metalization layers and vertical contacts to interconnect them in a mono-crystal silicon wafer, which serves as the substrate. Field of view size: 0.74 x 1.11 mm (0.029 x 0.044 in)